• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor fabrication process. In particular, in order to simultaneously form a Halo structure and an LDD structure in a CMOS transistor, forming an isolation layer defining an active region on a semiconductor substrate, Forming a gate oxide film on the substrate, forming a first well of a first conductivity type and a second well of a second conductivity type in each of the active regions, and forming a first gate electrode on the first well; Forming a second gate electrode positioned on the second well, sequentially forming first and second sidewall spacers on each side of the first and second gate electrodes, and Forming a high concentration impurity region of a second conductivity type, removing the second sidewall spacers of the first and second gate electrodes, and forming a first conductivity type in the second well. Forming a concentration impurity region, forming a low concentration impurity region of a first conductivity type in contact with the high concentration impurity region of the second well, and a first sidewall formed on each side of each of the first and second gate electrodes Removing the spacers, forming a second conductivity type halo region in contact with the low concentration impurity region of the second well, and forming a second conductivity type low concentration impurity region in contact with the high concentration impurity region of the first well; Include.
    公开号:KR19980056435A
    申请号:KR1019960075705
    申请日:1996-12-28
    公开日:1998-09-25
    发明作者:황현상
    申请人:문정환；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    MOS transistor manufacturing method
    1 is a manufacturing process diagram of a MOS transistor according to the prior art
    2 is a manufacturing process diagram of a MOS transistor according to the present invention.
    * Description of the main parts of the drawings
    50 semiconductor substrate 52 device isolation film
    54 gate oxide film 60 P well
    70: N well 62 72: gate electrode
    63,73: first sidewall spacer 64,74: second sidewall spacer
    65,75: high concentration impurity region 66,76: low concentration impurity region
    67: halo area
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor manufacturing process, and more particularly, to a MOS transistor manufacturing process of simultaneously forming a Halo structure and a LDD (Lightly Doped Drain) structure in a CMOS transistor (Complementary Netal On Silicon Transistor).
    In the manufacture of highly integrated circuits using MOS transistors, the length of the channel becomes shorter as the size of the MOS transistor decreases. As described above, in a short channel device having a short channel length, the two junctions are very close to each other, so that the depletion layers of the source and drain can penetrate into the channel even when no bias is applied. At this time, when the depletion region penetration of the source and the drain reaches an extreme state, two depletion regions meet and a punchthrough occurs so that the depletion region from the drain to the source continues.
    The electrons injected into the source are driven to the drain by a high field between the two electrodes, which supply high energy to the electrons in the channel, causing a hotelectron effect. The hot electrons in these channels tunnel and penetrate into the gate oxide film on the channel and are trapped in the oxide to shorten the maintenance period of the device and reduce reliability.
    Previously, an LDD structure has been proposed to solve the short channel effect and gradually reduce the doping concentration at the drain and channel boundary. The LDD structure suppresses the generation of hot electrons in the channel by reducing the high electric field between the drain and the channel region.
    The short channel problem can also be solved using the Halo architecture. This structure limits the influence of the induced electric field on the drain by a region formed deeper than the drain, ie oppositely-doped pockets, in a conductivity type opposite to the drain. Therefore, the punch-through voltage of the device can be increased, and the threshold voltage drop of the short channel can be reduced.
    Figure 1 shows a manufacturing process diagram of a MOS transistor according to the prior art, for example, US Patent No. 5,413,945 briefly shows only the main process.
    First, as shown in FIG. 1A, a device isolation film 12 defining an active region is formed in a semiconductor substrate 10, and then a gate oxide film 14 is formed insulating the gate electrode to be formed from the substrate. Form. Thereafter, p wells 20 for forming an NMOS and n wells 30 for forming a PMOS are formed, respectively. (Hereinafter, a p well region for forming an NMOS in a semiconductor substrate is referred to as an NMOS region. The n well region for forming is referred to as a PMOS region.) Then, a polysilicon layer is deposited on the entire surface, and then photo-etched to form gate electrodes 22/32 in the NMOS region and the PMOS region, respectively.
    Then, as shown in Fig. 1B, an ion implantation process of injecting n-ions into the substrate is performed to form n-regions 11n on both substrates of the gate electrodes 22/32, respectively. do. At this time, the substrate is inclined by 15 to 45 degrees, or the ion is implanted into the lower portion of the gate electrodes 22/32 by a titling process such as tilting the ion implanter. Accordingly, an n-region 11n underoverlap is formed on both sides of the gate electrode.
    Subsequently, as shown in Fig. 1C, after the photoresist pattern 16 covering the NMOS region is formed, an ion implantation process is performed in which p-ions are perpendicularly incident to the substrate, thereby forming n- formed in the PMOS region. A part of the region 11n is switched to the p-region 11p. Of course, the concentration of p-ion implanted at this time should be an amount that can sufficiently cover the already formed n-region. As a result of ion implantation, the n-region 11n under overlapping the gate electrode 32 of the PMOS region is not affected by the p-ion vertically incident using the gate electrode 32 as a mask, so the n-region ( 11n). Thereafter, the photoresist pattern 16 covering the NMOS region is removed for the next process.
    Then, as shown in Fig. 1D, an oxide film is formed on the entire surface, and then anisotropic etching is performed to form sidewall spacers 23/33 on both sides of each gate electrode 22/32. Form each.
    Subsequently, as shown in FIG. 1E, after forming the photoresist pattern 16 covering the PMOS region, an ion implantation process is performed in which n + ions are incident perpendicularly to the substrate, whereby the n + region 19n is formed in the NMOS region. ). Thereafter, the photoresist pattern 16 covering the PMOS region is removed for the next process.
    Subsequently, as shown in Fig. 1B, after forming the photoresist pattern 16 covering the NMOS region by the same method, an ion implantation process is performed in which p + ions are incident perpendicularly to the substrate to perform the implantation into the PMOS region. The p + region 19p is formed.
    Subsequently, as shown in FIG. 1 (G), when the entire substrate is heat treated to activate each ion region, diffusion of implanted ions proceeds. As a result, an LDD structure composed of a high concentration impurity region 25 and a local concentration impurity region 26 is formed in the NMOS region, and a high concentration impurity region 35 and a low concentration impurity region 36 and opposite conductivity types are formed in the PMOS region. The Halo structure which consists of the ion region 37 which has the branch is formed.
    In the conventional manufacturing process of the MOS transistor, the sidewall spacers of the NMOS and the PMOS are formed to have the same thickness. However, due to the material property, the lateral diffusion of the source / drain region formed of p + is much larger than the lateral diffusion of the source / drain region formed of n +. Therefore, when ion implantation is performed in the NMOS and the PMOS by forming sidewall spacers having the same thickness as a mask, the channel of the PMOS is shortened and the channel of the NMOS becomes relatively long. As a result, when a voltage is applied to such a MOS transistor, the characteristics of a short channel become deeper in a PMOS, and a driving current decreases in an NMOS.
    The present invention has been made to solve such a problem, and the channel of the PMOS is shortened to make the effective channel lengths of the PMOS and the NMOS the same, and the channel of the NMOS is formed long so that the operation of each device is smooth when the actual voltage is applied. I'm trying to.
    To this end, in the manufacturing process of the MOS transistor, the present invention provides a method of forming an isolation layer defining an active region on a semiconductor substrate, forming a gate oxide layer on the active region of the semiconductor substrate, Forming a first well of a first conductivity type and a second well of a second conductivity type, and forming a first gate electrode on the first well and a second gate electrode on the second well, respectively. Forming first and second sidewall spacers on side surfaces of each of the first and second gate electrodes, and sequentially forming the first and second gate electrodes and the first and second gate electrodes. Forming a high-concentration impurity region of a second conductivity type in said first well using a sidewall spacer as a mask, removing said second sidewall spacers of said first and second gate electrodes; Forming a high concentration impurity region of a first conductivity type in the second well using the first sidewall spacer of the second gate electrode and the second gate electrode as a mask, and contacting the high concentration impurity region of the second well; Forming a low concentration impurity region of a first conductivity type, removing a first sidewall spacer formed on each side of the first and second gate electrodes, and a second contacting the low concentration impurity region of the second well; Forming a conductive halo region and a second conductive impurity region in contact with the high concentration impurity region of the first well.
    Hereinafter, the present invention will be described with reference to the accompanying drawings.
    2 is a manufacturing process diagram of a MOS transistor according to the present invention.
    First, as shown in FIG. 2A, a device isolation film 52 defining an active region is formed in the semiconductor substrate 50, and then a gate oxide film 54 is formed so as to insulate the gate electrode to be formed from the substrate. Form. Subsequently, p wells 60 for forming an NMOS and n wells 70 for forming a PMOS are formed, respectively. (Hereinafter, a p well region for forming an NMOS in a semiconductor substrate is referred to as an NMOS region. The n well region for forming is referred to as a PMOS region.) Since the structure described above can be manufactured by a conventional method, description of the manufacturing process is omitted.
    Thereafter, gate electrodes 62/72 are formed on the upper ends of the NMOS region and the PMOS region. The gate electrode is formed by forming a polysilicon layer on the entire surface by LPCVD (Low Pressure Chemical Vapor Deposition), and then photo-etching the polysilicon layer in a predetermined shape. However, when the gate oxide film 54 positioned below the substrate is etched by the etchant during the photolithography process of the polysilicon layer to pattern the gate electrodes 62/72, the remaining gate oxide film 54 is removed. It is a good idea to carry out the refining process.
    Subsequently, as shown in FIG. 2B, after the nitride film is deposited on the entire surface, the nitride film is anisotropically photo-etched to form the first sidewall spacer 63 / on the sidewall of each gate electrode 62/72. (73) is formed. Subsequently, after the oxide film is deposited on the entire surface, the oxide film is anisotropically photo-etched to form second sidewall spacers 64/74 in contact with the side surfaces of the first sidewall spacers 63/73, respectively. As such, it is preferable that the first side wall spacers 63/73 and the second side wall spacers 64/74 circumscribed therebetween be formed of materials having different etching selectivities, which, in the next process, are used to form the second side wall spacers. This is to prevent over-etching from the etching process for removing the spacer to the first sidewall spacer.
    Subsequently, as shown in FIG. 2C, after the photoresist pattern 56 covering the NMOS region is formed, an ion implantation process perpendicular to the substrate is performed using p + to form p + in the PMOS region. Source / drain regions 75 are formed. In general, a boron or BF 2 having a dose of about 2 E15 to 5 E15 / cm 2 is injected into the substrate using an injection energy of 50 to 100 KeV. At this time, p + is injected into the semiconductor substrate 50 using the first sidewall spacer 73, the second sidewall spacer 74, and the gate electrode 72 as a mask. Thereafter, the photoresist pattern 56 is removed for the next process.
    Then, as shown in Fig. 2 (d), each second sidewall spacer 64/74 is removed. The second sidewall spacer is formed of an oxide film, and the first sidewall spacers 63/73 inscribed therein are formed of a nitride film. Therefore, the second sidewall spacers are etched by using the difference in their etching selectivity. An oxide etching material having a high etching selectivity for the nitride film is hydrofluoric acid.
    Subsequently, as shown in Fig. 2E, a photosensitive film pattern 56 covering the PMOS region is formed. Subsequently, an ion implantation process that is incident perpendicularly to the substrate using n + is performed to form a source / drain region 65 formed of n + in the NMOS region. In general, an asce (As) having a dose of about 2 E15 to 5 E15 / cm 2 is injected into the substrate using an injection energy of 50 to 100 KeV. At this time, the source / drain region 65 formed in the NMOS is ion-implanted using the first sidewall spacer 63 and the gate electrode 62 having the second sidewall spacer removed therein, and thus the source / drain region formed in the PMOS. The interval is less than 75.
    Then, as shown in Fig. 2B, an ion implantation step of implanting an acenic having a dose amount of about 2 E12 to 2 E12 / cm 2 into the substrate using an implantation energy of 50 to 70 KeV is performed. An n-region 66 pole and an LED region are formed inside the source / drain region 65 of the NMOS. At this time, ion implantation is performed by a tilting process such as rotating the substrate by inclining 15 to 45 degrees or tilting the ion implanter. Accordingly, the n-region 66 under overlapping the first sidewall spacer 63 is formed. Thereafter, the photoresist pattern 56 is removed for the next process.
    Subsequently, as shown in Fig. 2 (G), boron or BF 2 having a dose of about 2 E12 to 2 E12 / cm 2 is injected into the substrate without a mask by using an injection energy of 50 to 70 KeV. An ion implantation step is performed. At this time, p-ions are also implanted in the lower portion of the gate electrode by a titling process such as rotating the substrate by tilting the substrate 15 to 45 degrees or tilting the ion implanter to form a p-region under overlapping both sides of the gate electrode. Let's do it. As a result, a Halo structure is formed in the NMOS to surround the p-region 67 inside the n-region 66, and an LDD structure is formed in the PMOS to form the p-region 76 inside the p + region 75. .
    However, in the process of injecting n- described with reference to FIG. 2B, if the n-region 66 is thinly formed in the P well 60 of the NMOS region, FIG. The p- implantation process described with reference may form the p-region 67 surrounding the n-region 66 by a conventional ion implantation, rather than by a titling method.
    As described above, in the present invention, the channel of the PMOS can be formed long, so that not only the short channel effect can be reduced, but also the channel of the NMOS can be formed relatively short, so that the driving current can be improved. In addition, the number of times of using the photosensitive film pattern can be reduced as compared with the conventional art, and thus the photo process performed for this purpose is reduced, which is advantageous in the process.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] A method of manufacturing a MOS transistor, the method comprising: forming an isolation layer defining an active region in the semiconductor substrate, forming a gate oxide layer on the active region of the semiconductor substrate, and forming a first conductivity type in each of the active regions Forming a first well of the second well and a second well of a second conductivity type; forming a first gate electrode on the first well and a second gate electrode on the second well; And sequentially forming first and second sidewall spacers on side surfaces of the first and second gate electrodes, and masking the first and second sidewall spacers of the first gay electrode and the first gate electrode. Forming a high concentration impurity region of a second conductivity type in the first well, removing the second sidewall spacers of the first and second gate electrodes, And forming a high-concentration impurity region of a first conductivity type in the second well using the first sidewall spacer of the second gate electrode as a mask, and contacting the high-concentration impurity region of the second well. Forming a low concentration impurity region, removing a first sidewall spacer formed on each side of each of the first and second gate electrodes, and a second conductivity type halo region in contact with the low concentration impurity region of the second well; And forming a low concentration impurity region of a second conductivity type in contact with the high concentration impurity region of the first well.
    [2" claim-type="Currently amended] The method of claim 1, wherein the low concentration impurity region of the second well is formed by a titling process using the first sidewall spacers of the second gate electrode and the second gate electrode as a mask.
    [3" claim-type="Currently amended] 2. The method of claim 1, wherein the halo region and the low concentration impurity region of the first well are formed by a titling process using the first and second gate electrodes as masks.
    [4" claim-type="Currently amended] The method of manufacturing a MOS transistor according to claim 2 or 3, wherein the tettle process is performed at an angle of 15 to 45 degrees with the surface of the substrate.
    [5" claim-type="Currently amended] The method of claim 1, wherein the first sidewall spacer is formed of a nitride film.
    [6" claim-type="Currently amended] The method of claim 1, wherein the second sidewall spacer is formed of an oxide film.
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    同族专利:
    公开号 | 公开日
    KR100204800B1|1999-06-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-28|Application filed by 문정환, 엘지반도체 주식회사
    1996-12-28|Priority to KR1019960075705A
    1998-09-25|Publication of KR19980056435A
    1999-06-15|Application granted
    1999-06-15|Publication of KR100204800B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960075705A|KR100204800B1|1996-12-28|1996-12-28|Manufacturing method of the mos transistor|
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